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| Dual Channel High-IP3 100MHz - 6GHz Active Mixer Preliminary Technical Data FEATURES Dual Channel Up/Down Converter Power Conversion Gain of 1.5dB Wideband RF, LO, and IF ports SSB Noise Figure of 11dB SSB NF with +10dBm blocker of 20dB Input IP3 of 27dBm Input P1dB of 12 dBm Typical LO Drive of 0 dBm -40dBm LO Leakage at RF Low Current Operation: 5 V @ 200 mA Adjustable Bias for Low Power Operation Exposed Paddle 4 x 4 mm, 24 Lead LFCSP Package ADL5802 APPLICATIONS Cellular Base Station Receivers Main and Diversity Receiver Designs Radio Link Downconverters GENERAL DESCRIPTION The ADL5802 utilizes high linearity doubly balanced active mixer cores with integrated LO buffer amplifiers to provide high dynamic range frequency conversion from 100MHz to 6GHz. The mixers benefit from a proprietary linearization architecture which provides enhanced IP3 performance when subject to high input levels. A bias adjust feature allows the input linearity, SSB Noise Figure, and DC current to be optimized using a single control pin. The high input linearity allows the device to be used in demanding cellular applications where in-band blocking signals may otherwise result in degradation in dynamic performance. The balanced active mixer arrangement provides superb LO to RF and LO to IF leakage, typically better than -40dBm. The IF outputs are internally terminated to a 200- source impedance and provide a typical voltage conversion gain of 7.5 dB when loaded into a 200- load. Figure 1. Functional Block Diagram The ADL5802 is fabricated using a SiGe high performance IC process. The device is available in a compact 4mm x 4mm 24lead LFCSP package and operates over a -40C to +85C temperature range. An evaluation board is also available. REV. PrA Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. www.analog.com Tel: 781.329.4700 Fax: 781.326.8703 (c) 2008 Analog Devices, Inc. All rights reserved. ADL5802 ADL5802--Specifications Preliminary Technical Data Table 1. VS = 5 V, TA = 25C, fRF = 900 MHz, fLO = 703 MHz, LO power = 0 dBm, Zo = 50, unless otherwise noted Parameter RF INPUT INTERFACE Return Loss Input Impedance RF Frequency Range OUTPUT INTERFACE Output Impedance IF Frequency Range DC Bias Voltage LO INTERFACE LO Power Return Loss 1 Conditions Min Typ 12 50 Max Unit dB Tunable to >20dB over a limited bandwidth 100 Differential impedance, f = 200 MHz Can be matched externally to 3000MHz LF 4.75 -6 VS 0 12 50 200 6000 MHz 600 5.25 +6 MHz V dBm dB MHz Input Impedance LO Frequency Range DYNAMIC PERFORMANCE Power Conversion Gain Voltage Conversion Gain SSB Noise Figure SSB Noise Figure Under-Blocking Input Third Order Intercept Input Second Order Intercept Input 1 dB Compression Point LO to IF Output Leakage LO to RF Input Leakage RF to IF Output Isolation RFI1 to RFI2 Channel Isolation IF/2 Spurious POWER INTERFACE Supply Voltage Quiescent Current Disable Current Resistor Programmable ENBL pin low. -10 dBm Input Power Unfiltered IF Output Unfiltered IF Output +10dBm Blocker present +/-3MHz from wanted RF input, LO source filtered fRF1 = 889 MHz, fRF2 = 890 MHz, fLO = 690 MHz, each RF tone at -10 dBm fRF1 = 889 MHz, fRF2 = 890 MHz, fLO = 690 MHz, each RF tone at -10 dBm Excluding Transformer and PCB Losses ZSOURCE = 50, Differential ZLOAD = 200 Differential 100 6000 1.5 7.5 11 20 27 56 12 -65 -40 -28 50 -65 dB dB dB dB dBm dBm dBm dBm dBm dB dB dBc 5 200 160 V mA mA 1 Supply voltage should be applied from external circuit through choke inductors or IF Transformer center tap. REV. PrA | Page 2 of 8 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 2. Parameter Supply Voltage, VPOS PWDN, VSET RF Input Power, RF1+, RF1-, RF2+, RF2Internal Power Dissipation JA (Exposed Paddle Soldered Down) JC (At Exposed Paddle) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 5.5 V TBD TBD TBD TBD TBD TBD -40C to +85C -65C to +150C ADL5802 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION REV. PrA | Page 3 of 8 ADL5802 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Preliminary Technical Data Figure 2. Pin Configuration Table 2. Pin Function Descriptions Pin No. 1,2,5,8,14, 17,18, 21 3,4 6, 13, 24 7 9, 10 12 Mnemonic GND OP1+, OP1VPOS ENBL LOIP, LOIN VSET Function Device Common (DC Ground). Channel 1Mixer differential output terminals. Need to apply bias through pull-up choke inductors or center tap of the IF transfomer. Positive Supply Voltage. 5.0V Nominal Device Enable. Pull low to enable the device, pull high to disable. Differential LO input terminals. Internally matched to 50. Must be ac-coupled. High IP3 bias control. For high IP3 performance apply ~4V. Improved NF performance and lower supply current can be set by applying ~2V - 3V to the VSET pin. A resistor can be connected to the supply to raise the voltage while a resistor to GND will lower the voltage. Channel 2 Mixer differential output terminals. Need to apply bias through pull-up choke inductors or center tap of the IF transfomer. Differential RF input terminals for channel 2. Internally matched to 50. Must be ac-coupled. Differential RF input terminals for channel 1. Internally matched to 50. Must be ac-coupled. 15, 16 19. 20 22, 23 OP2+, OP2RF2+, RF2RF1+, RF1- REV. PrA | Page 4 of 8 Preliminary Technical Data TYPICAL PERFORMANCE CHARACTERISTICS-PRELIMINARY DATA VS = 5 V, TA = 25C, as measured using typical circuit schematic with low-side LO unless otherwise noted 4 ADL5802 20 3 VSET_3 V VSET_3.5 V VSET_4 V 18 16 Iset = 3.0V Iset = 3.5V Iset = 4.0V SSB Noise Figure (dB) 1000 1500 2000 2500 3000 3500 4000 2 14 12 10 8 6 4 2 Gain (dB) 1 0 -1 -2 500 RF Frequency (MHz) 0 500 1000 1500 2000 2500 3000 3500 4000 RF Frequency (MHz) Figure 3. Conversion Gain versus RF Frequency Figure 6. Single-Sideband NF versus RF Frequency 40 25 2.5V 3V 3.5V 4V Poly. (4V) Poly. (3.5V) Poly. (3V) Poly. (2.5V) 35 20 30 25 Single-Side Band NF(dB) 1500 2000 2500 3000 3500 4000 Input IP3 (dBm) 15 20 15 10 10 5 VSET_3 V VSET_3.5 V VSET_4 V 5 0 500 0 1000 -20 -15 -10 -5 0 5 10 RF Frequency (MHz) Blocker Level(dBm) Figure 4. IIP3 versus RF Frequency Figure 7. Single-Sideband NF versus Blocker Level at 1950MHz 16 -20 14 -25 VSET_3 V VSET_3.5 V VSET_4 V 12 LO to RF Leakage (dBm) -30 Input P1dB (dBm) 10 -35 8 -40 6 -45 4 VSET_3 V VSET_3.5 V -50 2 VSET_4 V 1000 1500 2000 2500 3000 3500 4000 -55 0 500 -60 300 800 1300 1800 2300 2800 3300 3800 RF Frequency (MHz) LO Frequency (MHz) Figure 5. IP1dB versus RF Frequency Figure 8. LO to RF Leakage versus LO Frequency REV. PrA | Page 5 of 8 Preliminary Technical Data 300 ADL5802 250 Supply Current (mA) 200 150 100 50 0 1.5 2 2.5 3 3.5 4 4.5 Vset (V) Figure 9. Supply Current vs. Vset 70 Channel to Channel Isolation (dB) 60 50 40 30 20 10 0 500 1000 1500 2000 2500 3000 3500 4000 RF Frequency (MHz) Figure 10. Channel to Channel Isolation vs. RF Frequency REV. PrA | Page 6 of 8 Preliminary Technical Data EVALUATION BOARD SCHEMATIC ADL5802 Figure 11. Evaluation Board Schematic. Table 3. Eval Board Configuration Components C1, C4, C6, C7, C8, C9, C10, C11, C17, C18, R10, R12, R19, R20, R21 Function Power Supply Decoupling. Nominal supply decoupling consists a 0.01 F capacitor to ground in parallel with 10pF capacitors to ground positioned as close to the device as possible. Series resistors are provided for enhanced supply decoupling using optional ferrite chip inductors. RF Channel 1 and Channel 2 Input Interfaces. Input channels are accoupled through C5, C12, C13 and C14. T3 and T4 are 1:1 baluns used to interface to the 50- differential inputs. IF Channel 1 and Channel 2 Output Interfaces. The 200- open collector IF output interfaces are biased through the center taps of 4:1 impedance transformers at T2 and T4. C15 and C16 provide local bypassing with R20 and R21 available for additional supply bypassing. L1, L2, L3, and L4 provide the options when pull-up choke inductors are used to bias the open-collector outputs. R6, R7, R13, R14, R15, and R16 are provided for IF filtering and matching options. LO Interface. C2 and C3 provide ac-coupling for the local oscillator input. T1 is a 1:1 balun to allow single-ended interfacing to the differential 50- local oscillator input. R4 and R5 provide the options when differential LO interfaces are needed. ENABLE Interface. The ADL5802 can be disabled using the 3-pin ENBL1 header. The ENBL pin is pulled up to VPOS through R9. R1 is provided as an optional termination for the high impendace enable interface. VSET Bias Control. R22 and R23 form an optional resistor divider network between VPOS and GND, allowing for a fixed bias setting. The default values are set up for 3.8 V at the VSET pin. Default Conditions C6, C7, C8 = 10pF (size 0402) C9, C10, C11 = 0.01 F (size 0402) C1, C4, C17, C18 = open (size 0402) R10, R12, R19, R20, R21 = 0 (size 0402) C5, C12, C13, C14 = 1nF (size 0402) T3, T5 = ETC1-1-13 (M/A-Com) C15, C16 = 100pF (size 0402) L1, L2, L3, L4 = open (size 0805) R2, R3, R13, R14, R15, R16, R20, R21 = 0 (size 0402) R6, R7 = open (size 0402) T2, T4 = TC4-1W+ (MiniCircuits) C2, C3 = 1nF (size 0402) R4, R5 = 0 (size 0402) T1 = ETC1-1-13 (M/A-Com) R9 = 10k (size 0402) R11 = 0 (size 0402) R1 = open (size 0402) ENBL1 = 3-pin header and shunt R22 = 866 (size 0402) R23 = 10k (size 0402) C5, C12, C13, C14, T3, T5, RF1, RF2 C15, C16, L1, L2, L3, L4, R2, R3, R6, R7, R13, R14, R15, R16, R20, R21, T2, T4, IF1, IF2 C2, C3, R4, R5, T1, LO R1, R9, R11, ENBL1 R22, R23, VSET REV. PrA | Page 7 of 8 ADL5802 OUTLINE DIMENSIONS Preliminary Technical Data Figure 12. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 4mm x 4mm Body, Very Thin Quad (CP-24-2)) Dimensions shown in millimeters ORDERING GUIDE Models ADL5802XCPZ-R7 ADL5802XCPZ-WP ADL5802-EVALZ Temperature Range -40C to +85C -40C to +85C Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Package Option CP-24-2 CP-24-2 Branding TBD TBD Transport Media Quantity TBD, Reel TBD, Waffle Pack 1 REV. PrA | Page 8 of 8 PR07882-0-10/08(PrA) |
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